1. Field of the Invention
The present invention is directed to a process and apparatus for automatically converting a design implemented with a programmable device into a design of a non-programmable device in a selected, specific, desired gate array technology and, more particularly, to a method and apparatus that automatically creates a behavioral model of the programmable device and a design of the device in a target technology, simulates both the model and the design which are then compared, thereby insuring that the behavior of the programmable logic, in which the device was designed, is the same as the behavior of the non-programmable logic implemented in the target gate array technology.
2. Description of the Related Art
Conventionally, logic devices are designed and tested (prototyped) using programmable logic or programmable gate array devices which are specifically designed to assist in the design of the logic device desired. Programmable devices are used for the prototypes and final designs because the devices can be easily reprogrammed during the design process whenever a mistake in the design of the device is discovered. Once the design using the programmable logic is completed and tested, if the manufacturer desires to produce the logic device in large quantities at a reduced cost, the design in the programmable logic must be converted into a design in the non-programmable target technology. This conversion is generally performed by engineers that specialize in the target technology and not the designers of the original device. The conventional method for converting from a programmable device to a specific gate array consists of manually entering a design into a computer aided engineering tool which is compatible or supports the target technology foundry and manually converting simulation results from the computer aided engineering tool in which the programmable device was designed into simulation results in the tool of the target foundry to provide a baseline to check the converted design. If after manual entry, if it is discovered that models for one or more of the parts within a programmable device design do not exist within the target foundry library, they must be created using target foundry parts. The only verification of a correct translation into the target gate array technology is the simulation output and any fault coverage less than 100 percent allows for undetected errors. That is, if the test vectors created for the original device do not test newly created models then the untested portion may not perform the function of the original design.